Data retention in operational and sleep modes

ABSTRACT

A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a bidirectional tristateable device, said bidirectional tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that said portion of said circuit is powered down, and a voltage difference across said retention latch and said bidirectional tristateable device is maintained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of data processing systems. Moreparticularly, this invention relates to circuits and methods ofoperating circuits that allow for the storage of a signal value in bothoperational and sleep modes.

2. Description of the Prior Art

In many circuits, particularly those that run off remote power suppliessuch as batteries, it is important to keep the power consumption of thecircuits low. As well as addressing the issue of operational circuitefficiency attention is also being turned to reducing static powerconsumption, i.e. power loss due to leakage currents. One way ofaddressing this is to provide the circuit with a sleep mode so that itis in effect powered down during these non-operational periods. Toreduce static power during these sleep periods, many circuit designs arenow making use of on-chip power gating which allows rapid transitionsbetween sleep and functional modes. This power gating is achieved byinserting power transistors between the targeted circuitry and Vddcreating a “virtual” Vdd rail, or by inserting power transistors betweenthe targeted circuitry and Vss creating a “virtual” Vss rail. To enter alow leakage mode, the power transistors are turned off and the leakageof the design is limited by the leakage of the power transistors. Sincethe power transistors can be made to be high Vt (threshold voltage), andsince the width of the power transistors can be much less than the widthof the active devices in the circuit, leakage currents can bedramatically reduced. Thus, when the power transistors are turned offthe virtual power rail at their output floats and the circuit is powereddown.

Although this results in substantial power savings it also results in aloss of state within the targeted circuitry. If it is desired that thecircuit retain state during sleep mode, data retention circuits such asspecial data retention flip-flops must be used within the design. Such amode of operation allows the stored signal values to be securely held ina small portion of the circuitry whilst the remainder of the circuitryis powered down for leakage reduction purposes. When power is resumed,the saved signal value is restored and operation continues.

A common prior art approach to data retention is to provide anadditional third storage or balloon latch that is not in the datapathway of the other two latches of a flip flop and to store data inthis third latch during sleep mode. This latch has its own power supplyand can be built of high threshold components. Such a system isdescribed in “A 1-V High Speed MTCMOS Circuit Scheme for Power-DownApplication Circuits” IEEE Journal of Solid-State Circuits, Vol 32, No6, June 1997. A disadvantage of this approach is that the balloonlatches consume considerable additional circuit area.

It has also been proposed for sense amplifier flip-flops and hybridlatch flip-flops which have associated scan cells that operate inaccordance with the level sensitive scan design methodology to reuse thescan cells for data retention during a power down mode of operation.Whilst this approach reduces the increase in circuit overhead associatedwith providing the data retention capability, it does require control ofthe three clock signals of the sense amplifier flip-flops or hybridlatch flip-flops with their known disadvantages in terms of speed, powerconsumption and other factors. It is also only applicable to flip flopshaving dedicated scan latches.

“Lower Power Integrated Scan-Retention Mechanism” ISPLED August 2002,also addresses this problem.

Co pending U.S. application Ser. No. 11/088268 having the same assigneeas this patent also addresses this problem.

SUMMARY OF THE INVENTION

A first aspect of the present invention provides a circuit for retaininga signal value during a sleep mode while a portion of said circuit ispowered down comprising: a clock signal input operable to receive aclock signal; at least one latch clocked by said clock signal; a datainput, a data output and a forward data path therebetween, wherein asignal value is operable to be received at said data input, is clockedinto said at least one latch and passes to said data output along saidforward data path; wherein at least one of said at least one latchcomprises a retention latch operable to retain a signal value duringsaid sleep mode; and said circuit further comprises a bidirectionaltristateable device, said bidirectional tristateable device beingarranged between said forward data path and said retention latch andbeing operable to selectively isolate said retention latch from saidforward data path in response to receipt of a first sleep signal;wherein in response to receipt of a second sleep signal, said secondsleep signal being received after said first sleep signal, said circuitis operable to enter said sleep mode such that a voltage differenceacross said portion of said circuit is reduced such that said portion ofsaid circuit is powered down, and a voltage difference across saidretention latch and said bidirectional tristateable device ismaintained.

The arrangement of the present invention that provides a data retentiondevice that can retain data in sleep mode and is not itself on theforward data path, is an effective way of retaining data without slowingthe critical timing path, which comprises the forward data path.Furthermore, the use of a tristateable device placed between the forwarddata path and the retention latch which can selectively isolate theretention latch, is a convenient way of retaining data in sleep mode andagain does not effect the critical timing path. Removing these devicesfrom the critical timing path allows the designer greater freedom in hisselection of components for these devices and therefore allows for theselection of, for example, low leakage components that may not have suchhigh performance.

Although it is possible for there to be only one latch, in mostembodiments the circuit comprises a plurality of latches clocked by saidclock signal, said signal value passing from one of said plurality oflatches to a subsequent one of said plurality of latches along saidforward data path, at least one of said plurality of latches comprisingsaid retention latch.

In some embodiments, said bidirectional tristateable device comprisestwo transistors operable to receive said first sleep signal and arrangedsuch that in response to receipt of said first sleep signal said twotransistors form a high impedance path and in response to not receivingsaid first sleep signal said two transistors form a low impedance path.

In other embodiments, said bidirectional tristateable device comprisesfour transistors, two of said four transistors forming saidbidirectional tristateable device and two of said four transistorsforming an inverter operable to invert said first sleep signal prior toinputting it to one of said two transistors.

Depending on whether an inverted sleep signal is available within thecircuit, the bidirectional tristateable device may be provided by two orfour transistors. In either case the provision of just a few transistorsis sufficient to adapt a traditional latch into a retention latch insome embodiments. Thus, a retention latch is achieved with a smallincrease in circuit area.

Although any sort of bidirectional tristateable device may be used, insome embodiments the bidirectional tristateable device comprises atransmission gate. Any tristateable devices that provide a low impedancein response to one input and a high impedance in response to anotherwould be appropriate, but a transmission gate is found to beparticularly effective.

In some embodiments, said data retention latch does not receive saidclock signal while in others said data retention latch is operable toreceive said clock signal.

Although it is possible to provide a latch circuit that is not clocked,it is found that one that is clocked can switch between states moreeasily and thus, may be preferred in some embodiments.

In some embodiments, said circuit further comprises clock signaldistribution means operable to distribute said clock signal to saidretention latch.

Although the clock signal may be generated outside of the circuit inothers it is generated within the circuit. Distributing the clock to theretention latch enables a clocked retention latch to switch state.

Although provision of the clocked signal to the retention latch enablesit to switch state more easily, it does have a drawback in that powerneeds to be supplied to the clock distribution in sleep mode and thiscan add significantly to static power loss.

In some embodiments, said clock signal distribution means comprises afirst sleep signal input operable to receive a first sleep signal;wherein in response to said first sleep signal said clock signaldistribution means is operable to hold said clock signal at apredetermined value such that said retention latch retains state.

Providing a clock signal at a predetermined value ensures the latch isin its data retaining recirculating mode.

Although the clock distribution means may comprise a number of forms, insome embodiments, said clock signal distribution means comprises a logicgate having a clock signal input and a first sleep signal input.

Such an arrangement is simple and yet allows the clock signal as seen bythe latches to be held at a predetermined value in response to the sleepsignal.

In some embodiments said clock signal distribution means comprises aplurality of components through which a clock signal propagates, saidcircuit is operable to reduce a voltage difference across saidcomponents of said clock signal distribution means upstream in a clocksignal propagation direction of said first sleep signal input such thatsaid components are powered down in response to said first sleep signal,and to maintain a voltage difference across said components downstreamof said first sleep signal input.

Power needs to be supplied to some of the clock distribution devices inorder to ensure that the signal value is held at said predeterminedvalue. The above arrangement allows much of the clock distributiondevices to be powered down, while ensuring the clock signal is kept atthe desired value.

In some embodiments, said retention latch comprises a clocked tristateinverter, and transistors arranged in parallel with a portion of saidclocked tristate inverter and operable to receive said first sleepsignal such that said retention latch is operable to retain stateirrespective of a value of said clock during receipt of said first sleepsignal.

One disadvantage with some embodiments of the present invention is thatthe clock signal to the retention latch needs to be maintained in orderfor the latch to remain in a recirculating mode. The clock distributionlogic which distributes the clock signal to the different componentscomprises components that are often not low leakage components and whichthus can use a lot of power. Thus, it is a considerable disadvantage tostatic power loss if power needs to be maintained to this part of thecircuit during sleep mode. The provision of additional components whichallow the clocked tristate inverter to retain state irrespective of theclock signal can therefore be very advantageous, as it allows the clocksignal distribution logic to be powered down during sleep mode andtherefore avoids or at least reduces power loss due to this part of thecircuit.

In some embodiments, said transistors comprise two transistors inparallel with said two clocked transistors of said tristate inverter,said two transistors receiving said first sleep signal and an invertedfirst sleep signal respectively.

The advantages of reduced power loss due to enabling the clock circuitto be powered down in sleep mode can be achieved with just twoadditional transistors. Thus, a small increase in circuit area can leadto the advantages of a relatively high reduction in static powerconsumption.

In some embodiments, said circuit comprises at least one further latch,at least two of said latches comprising a master slave flip flopcomprising a master latch and a slave latch, said retention latchcomprising said slave latch.

Although the retention latch can comprise any latch, for example aglitching element, a latch within a master slave flip flop is found tobe particularly advantageous. Furthermore, although the retention latchcould be formed from the master latch of such a flip-flop, generally itis formed from the slave latch. It should be noted that whatever latchit is formed from it should be in “look aside” mode, i.e. it should notbe located on the forward data path.

In some embodiments, said master slave flip flop comprises a resetmaster slave flip flop, said retention latch comprising two transistorsoperable to receive said first sleep signal and a reset signal andoperable to block said reset signal and prevent it from resetting astate of said retention latch in response to receipt of said first sleepsignal.

Although the retention latch may be formed within a reset flip flop, ifit is there are additional potential problems that need to be addressed.The potential problems relate to the possibility of the reset signalbeing inadvertently activated on entering or leaving sleep mode suchthat the retention latch is reset and the data that it should retain islost. Thus, in embodiments of the invention which utilise reset flopsadditional transistors may be used which block the reset signal fromaffecting the retention latch during sleep mode. Controlling theadditional transistors with a first sleep signal which is activatedbefore the second sleep signal ensures that the reset signal is held lowwhile the portion of the circuit is powered down.

A similar problem may occur with set master slave flip flops and thusembodiments of the present invention provide a circuit wherein saidmaster slave flip flop comprises a set master slave flip flop, saidretention latch comprising two transistors operable to receive saidfirst sleep signal and a set signal and operable to block said setsignal and prevent it from setting a state of said retention latch inresponse to receipt of said first sleep signal.

Additional transistors can also be used to prevent these set signalsfrom changing the data stored in the retention latch.

In some embodiments, the power supplied to the circuit is supplied fromoutside of the circuit, while in other embodiments the circuit comprisesa voltage regulator operable to control a voltage level supplied toportions of said circuit, said voltage regulator being operable toreceive said second sleep signal and in response to said second sleepsignal to reduce a voltage difference across said portion of saidcircuit such that said portion of said circuit is powered down; and tomaintain a voltage difference across said retention latch and saidbidirectional tristateable device.

In some embodiments, said circuit is operable to be powered in responseto a voltage difference applied across said circuit, said circuitfurther comprising a power transistor, said power transistor beingarranged such that said voltage difference is applied across said powertransistor and said portion of said circuit in series, said powertransistor being operable to receive said second sleep signal and beingoperable to be turned off in response to said second sleep signal, suchthat a voltage difference across said portion of said circuit is reducedand said portion of said circuit is powered down in response to saidsecond sleep signal.

Although the sleep state of the portion of the circuit that is powereddown can be achieved in a number of ways, power transistors are simpleand effective ways of achieving this sleep state which have very lowstatic power loss.

In embodiments of the invention said retention latch and saidbidirectional tristateable device comprise low leakage devices.

As the retention latch and tristateable device are continually powered,it is highly advantageous to make them from low leakage components suchas devices having a high threshold voltage. This means that there isvery little static power loss from these components. Furthermore, asthese components are arranged to be not on the forward data path i.e.not on the critical timing path the provision of low leakage componentsin this pathway does not affect the performance of the circuit.

In some embodiments, the circuit comprises a plurality of retentionlatches.

A plurality of retention latches for storing a plurality of signals insleep mode can be provided within the circuit.

In some embodiments, said circuit further comprises a plurality ofportions each comprising at least one retention latch.

A device can comprise a plurality of portions each having its ownretention latch. These can be controlled by the same sleep signals orthe circuit can be controlled by a plurality of different sleep signalssuch that different portions of the circuit can enter sleep mode and bepowered down at different times.

A further aspect of the present invention provides a method of storing asignal value within a circuit during a sleep mode while a portion ofsaid circuit is powered down, said method comprising the steps of:distributing said clock signal to a clock input of at least one latch,said at least one latch being located between a data input and a dataoutput such that a signal value received at said data input, is clockedinto said at least one latch and passes to said data output along aforward data path, and at least one of said at least one latch is aretention latch operable to retain a signal value during said sleepmode; wherein in response to a first sleep signal: isolating saidretention latch from said forward data path using a bidirectionaltristateable device located between said forward data path and saidretention latch; in response to a second sleep signal: reducing avoltage difference across said portion of said circuit such that saidportion of said circuit is powered down; and maintaining a voltagedifference across said retention latch and said bidirectionaltristateable device.

A yet further aspect of the present invention provides A circuit forretaining a signal value while a portion of said circuit is powered downcomprising: a clock signal input operable to receive a clock signal; ameans for retaining data clocked by said clock signal and comprising: aforward data path such that a signal value passes from a data input andis clocked into a retention means and passes to a data output along saidforward data path; said retention means being operable to retain asignal value during a sleep mode; and a bidirectional tristateable meansfor selectively isolating said retention means from said forward datapath in response to receipt of a first sleep signal, said bidirectionaltristateable means being arranged between said forward data path andsaid retention means; wherein in response to receipt of a second sleepsignal, said second sleep signal being received after said first sleepsignal, said circuit is operable to enter said sleep mode such that avoltage difference across said portion of said circuit is reduced suchthat said portion of said circuit is powered down, and a voltagedifference across said retention means and said bidirectionaltristateable means is maintained.

The above, and other objects, features and advantages of this inventionwill be apparent from the following detailed description of illustrativeembodiments which is to be read in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a master slave flip flop according to theprior art;

FIG. 2 schematically shows a master slave retention flip flop accordingto a first embodiment of the present invention and a timing diagram ofits operation;

FIG. 3 shows the component transistors of transmission gate 50 of FIG.2;

FIG. 4 shows the component transistors of an amended tristate inverterof the slave latch of a second embodiment of the present invention;

FIG. 5 schematically shows a master slave retention flip flop accordingto the second embodiment of the present invention and a timing diagramof its operation;

FIG. 6 schematically shows a reset master slave flip flop according tothe prior art;

FIG. 7 schematically shows a reset master slave retention flip flopaccording to an embodiment of the present invention and a timing diagramof its operation;

FIG. 8 shows the component transistors of an amended tristate inverterof the slave latch of the reset master slave retention flip flop of FIG.7;

FIG. 9 a shows the slave latch of a set master slave flop according tothe prior art;

FIG. 9 b shows the slave latch of a set retention master slave flopaccording to an embodiment of the present invention;

FIG. 10 shows a single retention latch according to an embodiment of thepresent invention; and

FIG. 11 shows a master slave flop, wherein the retention latch comprisesthe master latch.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows in schematic form a basic master slave flip flop accordingto the prior art. This basic master slave flop 20 has a clockdistribution means 10 which comprises a plurality of inverters operableto deliver different clock signals, clk, nclk an inverted form of clk,and bclk an inverted form of nclk. The basic master slave flop has aforward data path 23, between data input 21 and data output 29. Thisforward data path takes data from the input to a master latch 26 viatransmission gate 22 and to slave latch 28 via transmission gate 24.Transmission gates 22 and 24 are tristateable devices able to provide alow impedance data path or a high impedance data path depending on theclock values at their inputs. Thus, they act to either isolate thelatches or to allow transmission of data to them.

FIG. 2 shows a master slave retention flop 30 according to an embodimentof the present invention. This is an adaptation of the flop of FIG. 1and is able to provide data retention within the slave latch during a“sleep mode” when a portion of the flop is powered down.

This embodiment comprises clock distribution logic 10 and additionallyretention signal (ret) or first sleep signal distribution logic 12.These logic blocks are not powered down in sleep mode and this isindicated in the figure by the shading. Master slave retention flop 20comprises a forward data path between data input 31 and data output 39.The forward data path 33 takes data from the input 31 to master latch 36and then to slave latch 40. It comprises transmission gates 32 and 34between the data input 31 and the master latch 36 and between the master36 and slave latch 40 respectively.

Slave latch 40 also acts in this embodiment as the data retention latchand is selectively isolated from forward data path 33 by a bidirectionaltristateable device 50. The slave lo latch 40 and bidirectionaltristateable device 50 are not powered down in sleep mode and this isindicated in the figure by the shading. In this case bidirectionaltristateable device 50 is a transmission gate, although anybidirectional tristateable device operable to selectively provide highor low impedance and operable to drive a signal in either directionwould be suitable. Unlike transmission gates 32 and 34 transmission gate50 receives the retention and inverted retention signals from retentionor sleep signal distribution logic 12 as its control signals.Transmission gate 50 is responsive to these signals to either offer alow impedance state such that the slave latch 40 is in datacommunication with the forward data path 33 when the retention signal islow, or in response to the retention signal going high to offer a highimpedance state such that the slave latch 40 is isolated from theforward data path 33.

Slave latch 40 comprises an inverter 42 and a tristate inverter 44. Thetristate inverter 44 is clocked by clock signals sent from clock signaldistribution logic 10. It is for this reason that clock signaldistribution logic must always be powered up in this embodiment toensure that the recirculating path within the slave latch 40 is drivenand remains closed.

FIG. 2 also shows a timing diagram giving the values of the masterclock, clk signal, the first sleep signal which corresponds to theretention signal ret and the second sleep signal which provides anindication to portions of the circuit to power down. It also shows thestates that these signals put the flop into, that is the functional, thelow leakage and the intermediate states of this master slave retentionflop.

FIG. 3 shows transmission gate 50 of FIG. 2 in transistor form. Thisshows a preferred embodiment of the transmission gate. Clearly, anytristateable device that can selectively isolate the slave latch 40 fromthe forward data path 33 would be suitable. However, this preferredembodiment comprises just two transistors (four if the sleep signal, retneeds to be inverted and is not supplied to the circuit in invertedform) and thus, does not increase the circuit area of the flop by alarge amount.

One drawback of the embodiment of FIG. 2 is that the clock distributionlogic 10 needs to retain power in order for the slave or retention latch40 not to lose state. FIG. 4 shows a second embodiment giving analternative arrangement for the tristate inverter 44 of FIG. 2. In thisalternative arrangement, an additional two transistors 46 and 48 havebeen added in parallel to the clocked transistors of the tristateinverter 44. These two transistors receive the retention signal and theinverted retention signal from retention signal logic 12. By placingthese two transistors in this position, the retention of the data withinslave latch 40 can be assured provided the retention signal is highwhatever the values of the clock signals. Thus, data can be retainedeven if clock signal distribution logic is turned off. This ability toturn the clock signal distribution logic off can provide a large savingin power to the circuit as clock distribution signal logic is generallynot made of high Vt (threshold voltage) devices and is quite largethereby consuming a relatively large amount of static power.

An alternative to this (not shown) would be to hold the clock signal oftristate inverter 44 using logic and the sleep signal ret, therebyensuring that the circulating loop of the retention latch stays open anddata is retained without the need to run the clock signal continuously.A disadvantage of this is that at least some of the clock signaldistribution logic would need to be powered so there is more power lossthan the embodiment of FIG. 4.

FIG. 5 shows the master slave retention form of the second embodimentcomprising the tristate inverter 44 of FIG. 4. This diagram also shows atiming diagram relating to the operation of the master slave retentionflop 30 of this second embodiment. This timing diagram shows how in thelow leakage or sleep state the value of the clock signal is unimportantand thus, clock distribution logic can be turned off. In this embodimentit is just sleep signal distribution logic 12, slave latch 40 andtransmission gate 50 which are powered up in sleep mode. This embodimenttherefore allows a significant power saving at a cost in area of justtwo transistors compared to the embodiment of FIG. 2. This embodimenthas an additional six transistors compared to the prior art master slaveflop of FIG. 1 which had no retention capabilities.

FIG. 6 shows a reset master slave flop according to the prior art. Dataretention during sleep mode can be particularly difficult if theretention latch is a latch within a set or reset flip flop. This isbecause when powering up great care must be taken that the latch storingthe data is not set or reset before that data has been extracted,otherwise, the data could be lost on power up and its retention willthen have been worthless. As can be seen from FIG. 6, the slave latch 60comprises a NAND gate 63 in parallel with tristate inverter 64.

FIG. 7 shows a reset master slave retention flop according to anembodiment of the present invention. In this embodiment, slave orretention latch 60 comprises tristate inverter 64 adapted to retainstate even when the clock signal is turned off, in a similar way to theretention latch shown in FIG. 5. Thus, clock distribution logic 10 doesnot have to be powered up during sleep mode. It should be clear to theskilled person that slave latch 60 could comprise a standard tristateinverter such as that shown in FIG. 2, in which case the clockdistribution logic would need to retain power during sleep mode. Inaddition to clock signal distribution logic 10 and sleep signaldistribution logic 12 there is reset distribution logic 14 that isoperable to distribute a reset signal rst, and an inverted reset signal,nrst, to appropriate parts of the circuit. In addition to NAND gate 63equivalent to NAND gate 63 of FIG. 6 there is additional logic 66 on thereset signal input to this NAND gate. This logic 66 ORs the invertedreset signal nrst with the sleep signal ret and thereby assures that theretention latch 60 is not accidentally reset either on entry into orexit from sleep mode.

FIG. 8 shows gate 66 in transistor form. Specifically, the addition oftwo sleep transistors 65 and 67 which have the ret signal on theirinputs and thereby impede the reset signal from going high during sleepmode transform NAND gate 63 to OAI12 66.

FIG. 9 shows a corresponding embodiment for a set flop. FIG. 9 a showsthe slave latch 70 of a conventional set flop. In this set flop, a NORgate 73 is placed in parallel with the tristate inverter 74 of slavelatch 70. Slave latch 70 corresponds to slave latch 60 of the reset flopof FIG. 6, for a set flop. FIG. 9 b shows how an addition of two nretFETs 75 and 77 can transform NOR gate 73 to an A0112 gate 70. Theseadditional transistors 75 and 77 act like the transistors 65 and 67 ofthe reset flop to impede the set signal from being asserted during sleepmode.

FIG. 10 shows an embodiment of the present invention comprising a singleretention latch 70 that is not clocked. It should be noted that althougha tristate inverter is advantageous within the latch as it allows forthe state of the latch to be easily switched, it is not essential and anunclocked latch comprising inverters arranged in a loop such as thatshown as 70 in FIG. 10 is possible. In this embodiment the retentionlatch 70 and sleep signal distribution logic 12 retain power duringsleep mode. The clock distribution logic, however, does not retain powerin this embodiment.

FIG. 11 shows an alternative embodiment where retention latch 80comprises the master latch of a master/slave flop. This embodimentcorresponds to the clocked embodiment of FIG. 2 and clock distributionlogic 10, sleep signal distribution logic 12 and retention latch 80retain power during sleep mode.

It should be noted that all flops are shown as having inverters on theforward data path, but it should be clear to the skilled person thatthey could equally well be built with non-inverters in which case anadditional inverter would be needed at the end of the forward data path33. It should be clear to a skilled person that such alternativeembodiments fall within this scope of the present invention as definedin the appended claims.

Although illustrative embodiments of the invention have been describedin detail herein with reference to the accompanying drawings, it is tobe understood that the invention is not limited to those preciseembodiments, and that various changes and modifications can be effectedtherein by one skilled in the art without departing from the scope andspirit of the invention as defined by the appended claims

1. A circuit for retaining a signal value during a sleep mode while aportion of said circuit is powered down comprising: a clock signal inputoperable to receive a clock signal; at least one latch clocked by saidclock signal; a data input, a data output and a forward data paththerebetween, wherein a signal value is operable to be received at saiddata input, is clocked into said at least one latch and passes to saiddata output along said forward data path; wherein at least one of saidat least one latch comprises a retention latch operable to retain asignal value during said sleep mode, and said circuit further comprisesa bidirectional tristateable device, said bidirectional tristateabledevice being arranged between said forward data path and said retentionlatch and being operable to selectively isolate said retention latchfrom said forward data path in response to receipt of a first sleepsignal; wherein in response to receipt of a second sleep signal, saidsecond sleep signal being received after said first sleep signal, saidcircuit is operable to enter said sleep mode such that a voltagedifference across said portion of said circuit is reduced such that saidportion of said circuit is powered down, and a voltage difference acrosssaid retention latch and said bidirectional tristateable device ismaintained.
 2. A circuit according to claim 1, comprising a plurality oflatches clocked by said clock signal, said signal value passing from oneof said plurality of latches to a subsequent one of said plurality oflatches along said forward data path, at least one of said plurality oflatches comprising said retention latch.
 3. A circuit according to claim1, wherein said bidirectional tristateable device comprises twotransistors operable to receive said first sleep signal and arrangedsuch that in response to receipt of said first sleep signal said twotransistors form a high impedance path and in response to not receivingsaid first sleep signal said two transistors form a low impedance path.4. A circuit according to claim 1, wherein said bidirectionaltristateable device comprises four transistors, two of said fourtransistors forming said bidirectional tristateable device and two ofsaid four transistors forming an inverter operable to invert said firstsleep signal prior to inputting it to one of said two transistors.
 5. Acircuit according to claim 4, wherein said bidirectional tristateabledevice comprises a transmission gate.
 6. A circuit according to claim 1,wherein said retention latch is operable to receive said clock signal.7. A circuit according to claim 6, said circuit further comprising:clock signal distribution means operable to distribute said clock signalto said retention latch.
 8. A circuit according to claim 7, said clocksignal distribution means comprising a first sleep signal input operableto receive a first sleep signal; wherein in response to said first sleepsignal said clock signal distribution means is operable to hold saidclock signal at a predetermined value such that said retention latchretains state.
 9. A circuit according to claim 7, wherein said clocksignal distribution means comprises a logic gate having a clock signalinput and a first sleep signal input.
 10. A circuit according to claim8, wherein said clock signal distribution means comprises a plurality ofcomponents through which a clock signal propagates, said circuit isoperable to reduce a voltage difference across said components of saidclock signal distribution means upstream in a clock signal propagationdirection of said first sleep signal input such that said components arepowered down in response to said first sleep signal, and to maintain avoltage difference across said components downstream of said first sleepsignal input.
 11. A circuit according to claim 6, wherein said retentionlatch comprises a clocked tristate inverter, and transistors arranged inparallel with a portion of said clocked tristate inverter and operableto receive said first sleep signal such said retention latch is operableto retain state irrespective of a value of said clock during receipt ofsaid first sleep signal.
 12. A circuit according to claim 11, whereinsaid transistors comprise two transistors in parallel with said twoclocked transistors of said tristate inverter, said two transistorsreceiving said first sleep signal and an inverted first sleep signalrespectively.
 13. A circuit according to claim 1, said circuitcomprising at least one further latch, at least two of said latchescomprising a master slave flip flop comprising a master latch and aslave latch, said retention latch comprising said slave latch.
 14. Acircuit according to claim 13, wherein said master slave flip flopcomprises a reset master slave flip flop, said retention latchcomprising two transistors operable to receive said first sleep signaland a reset signal and operable to block said reset signal and preventit from resetting a state of said retention latch in response to receiptof said first sleep signal.
 15. A circuit according to claim 13, whereinsaid master slave flip flop comprises a set master slave flip flop, saidretention latch comprising two transistors operable to receive saidfirst sleep signal and a set signal and operable to block said setsignal and prevent it from setting a state of said retention latch inresponse to receipt of said first sleep signal.
 16. A circuit accordingto claim 1, said circuit further comprising a voltage regulator operableto control a voltage level supplied to portions of said circuit, saidvoltage regulator being operable to receive said second sleep signal andin response to said second sleep signal to reduce a voltage differenceacross said portion of said circuit such that said portion of saidcircuit is powered down; and to maintain a voltage difference acrosssaid retention latch and said bidirectional tristateable device.
 17. Acircuit according to claim 1, said circuit being operable to be poweredin response to a voltage difference applied across said circuit, saidcircuit further comprising a power transistor, said power transistorbeing arranged such that said voltage difference is applied across saidpower transistor and said portion of said circuit in series, said powertransistor being operable to receive said second sleep signal and beingoperable to be turned off in response to said second sleep signal, suchthat a voltage difference across said portion of said circuit is reducedand said portion of said circuit is powered down in response to saidsecond sleep signal.
 18. A circuit according to claim 1, wherein saidretention latch and said bidirectional tristateable device comprise lowleakage devices.
 19. A circuit according to claim 1, comprising aplurality of retention latches.
 20. A method of storing a signal valuewithin a circuit during a sleep mode while a portion of said circuit ispowered down, said method comprising the steps of: distributing saidclock signal to a clock input of at least one latch, said at least onelatch being located between a data input and a data output such that asignal value received at said data input, is clocked into said at leastone latch and passes to said data output along a forward data path, andat least one of said at least one latch is a retention latch operable toretain a signal value during said sleep mode; wherein in response to afirst sleep signal: isolating said retention latch from said forwarddata path using a bidirectional tristateable device located between saidforward data path and said retention latch; in response to a secondsleep signal: reducing a voltage difference across said portion of saidcircuit such that said portion of said circuit is powered down; andmaintaining a voltage difference across said retention latch and saidbidirectional tristateable device.
 21. A circuit for retaining a signalvalue while a portion of said circuit is powered down comprising: aclock signal input operable to receive a clock signal; a means forretaining data clocked by said clock signal and comprising: a forwarddata path such that a signal value passes from a data input, is clockedinto a retention means and passes to a data output along said forwarddata path and; said retention means being operable to retain a signalvalue during a sleep mode; and a bidirectional tristateable means forselectively isolating said retention means from said forward data pathin response to receipt of a first sleep signal, said bidirectionaltristateable means being arranged between said forward data path andsaid retention means; wherein in response to receipt of a second sleepsignal, said second sleep signal being received after said first sleepsignal, said circuit is operable to enter said sleep mode such that avoltage difference across said portion of said circuit is reduced suchthat said portion of said circuit is powered down, and a voltagedifference across said retention means and said bidirectionaltristateable means is maintained.